1. Field of the Invention
The present invention relates to a field MOS transistor used in a discrete semiconductor device or a high-voltage semiconductor integrated circuit, as well as to a semiconductor integrated circuit including the field MOS transistor.
The field MOS transistor is a MOS transistor which uses, as a gate insulating film, a comparatively-thick field insulating film formed on a semiconductor device. The field MOS transistor is used with a circuit requiring a high gate voltage, by means of utilization of the thickness of the gate insulating film. The field MOS transistor is used as a discrete semiconductor device in an application in which a signal is amplified or modified in accordance with a high gate voltage. In the field of a high-voltage semiconductor integrated circuit, the field MOS transistor is used as a sense element for sensing a high output voltage produced by a digital switching element or a gate protection element located in an integrated circuit.
2. Background Art
FIG. 9 shows the configuration of a related-art field MOS transistor of this type. An island region 2A is formed by means of surrounding, with a P+-isolation layer 3 and a P-well layer 4, a certain area in an Nxe2x88x92-epitaxial layer 2 formed on a Pxe2x88x92-type semiconductor substrate 1. An N-channel field MOS transistor is fabricated in the island region 2A. The N-channel field MOS transistor is constituted of a P-well 4A formed in a surface portion of the island region 2A, and an N-source region 5 and an N-drain region 6, which are formed in the P-well 4A. A gate electrode 10 is formed on a field insulating film 9 formed on the P-well 4A and between the source region 5 and the drain region 6. A source electrode 11 supplies a back-gate potential to the P-well 4A by way of a P+-diffusion layer 7 and is in contact with the source region 5. Further, a drain electrode 12 is in contact with the drain region 6 by way of the N+-diffusion layer 8.
In the configuration of the related-art field MOS transistor shown in FIG. 9, a junction withstand voltage between the drain region 6 and the P-well 4A determines the element withstand voltage of the overall transistor. The P-well 4A has the same doping level as that of the P-well 4 used for isolating the island region 2A. The doping level is comparatively high, and hence the element withstand voltage cannot be increased to a sufficiently high level. In a CMOS integrated circuit, the P-well 4A is often used for supplying a back-gate voltage to a CMOS transistor. From the viewpoint of preventing occurrence of parasitic operation and a punch-through phenomenon, the P-well 4 is set to a comparatively high doping level.
The configuration of such a related-art field MOS transistor imposes limitations on improvement of an element withstand voltage.
Hence, implementation of a field MOS transistor having a sufficient withstand voltage is difficult. For example, a circuit such as that shown in FIG. 3, an inverter circuit, or an analog circuit, any of which requires an element withstand voltage equal to the maximum gate voltage, usually requires a withstand voltage ranging from several tens of volts to one hundred and several tens of volts.
However, implementation of such an element withstand voltage using the configuration of the related-art field MOS transistor is impossible.
Philips Electronics has put forward a method of forming an N+-diffusion region in the island region 2A of the Nxe2x88x92-epitaxial layer 2, thus fabricating a high-withstand-voltage diode between the N+-diffusion region and the P-type semiconductor substrate 1. The configuration of, a high-withstand-voltage diode is introduced as a RESURF diode in Philips Journal of Research (Vol. 35, No.1, 1980, pp. 1 through 5). The journal shows that a high withstand voltage can be achieved by means of reducing the concentration of an epitaxial layer. The journal shows the configuration of a high-withstand-voltage diode, but fails to show a technique for increasing the withstand voltage of a field MOS transistor.
The present invention proposes a new field MOS transistor enabling an improvement in element withstand voltage, and a semiconductor integrated circuit including the field MOS transistor.
According to one aspect of the present invention, a field MOS transistor comprises a semiconductor substrate of first conductivity type and an epitaxial layer of second conductivity type formed on the semiconductor substrate. A field insulating film is formed on the epitaxial layer. A heavily-doped isolation layer of first conductivity type is formed in a predetermined location on the semiconductor substrate and surrounds an island region of the epitaxial layer. A lightly-doped isolation layer of first conductivity type is formed on the heavily-doped isolation layer, and the lightly-doped isolation layer, along with the heavily-doped isolation layer, surrounds the island region of the epitaxial layer. A channel formation region is formed so as to be joined to a lower surface of the field insulating film, and has substantially the same doping level as that of the lightly-doped isolation layer. A gate electrode is formed on the field insulating film above the channel formation region. Further, a source region and a drain region of second conductivity type are respectively formed within the island region of the epitaxial layer and on the opposite sides of the channel formation region.
In another embodiment of the present invention, the field MOS transistor preferably comprises an extended region which has substantially the same doping level as that of the heavily-doped isolation layer and extends below the island region of the epitaxial layer, and the channel formation region is formed preferably on the extended region. Further, the extended region may preferably be extended from the heavily-doped isolation layer.
According to another aspect of the present invention, a field MOS transistor comprises a semiconductor substrate of first conductivity type and an epitaxial layer of second conductivity type formed on the semiconductor substrate. A field insulating film is formed on the epitaxial layer. A heavily-doped isolation layer of first conductivity type is formed in a predetermined location on the semiconductor substrate and surrounds an island region of the epitaxial layer. A lightly-doped isolation layer of first conductivity type is formed on the heavily-doped isolation layer, and the lightly-doped isolation layer, along with the heavily-doped isolation layer, surrounds the island region of the epitaxial layer. An embedded layer of second conductivity type is formed below an island region of the epitaxial layer. Another embedded layer of first conductivity type is formed on the embedded layer of second conductivity type, and has substantially the same doping level as that of the heavily-doped isolation layer. A channel formation region of first conductivity type is formed on the embedded layer of first conductivity type so as to be joined to a lower surface of the field insulating film, and the channel formation region has substantially the same doping level as that of the lightly-doped isolation layer. A gate electrode is formed on the field insulating film above the channel formation region. Further, a source region and a drain region of second conductivity type are respectively formed on the embedded layer of first conductivity type and on the opposite sides of the channel formation region.
Other and further objects, features and advantages of the invention will appear more fully from the following description.